The field of the invention relates in general to a fast-dump structure for a solid-state image sensor that can be used to selectively dump charge from the main array of the device. In particular, this invention relates to image sensors of the frame transfer or full-frame type, which incorporate lateral-overflow drains (LODs) for blooming protection.
The fast-dump structure is typically used within prior art devices in the transition area between the vertical and horizontal CCD as shown in FIG. 1. The fast-dump can be used to selectively dump charge from the main array of the device before transfer is made into the horizontal register for effective and fast subsampling of and fast subsampling of the image. These structures can be located at every column of the vertical imaging section, or only at specific locations, (i.e., specific rows and/or columns), as predetermined at the time of design as described in U.S. Pat. No. 5,440,343. However, such prior art devices typically require a contact be made directly to the drain regions of each such structure, thereby putting obvious limitations on the cell sizes that can be realized for a given set of design rules. Although other types of fast-dump structures exist that eliminate the need for a separate contact at each column, such as described in our U.S. Pat. No. 6,507,056 and shown in FIG. 2, these structures have the disadvantage that charge must be transferred through the horizontal shift register which slows down the process.
Other prior art structures, such as described in our Ser. No. 09/533,050, get around the requirement to have a contact at each separate drain by providing a long fast-dump gate and drain below and adjacent the horizontal CCD. However, these types of structures require that charge be transferred through the horizontal CCD and subsequently into the fast-dump structure positioned beneath the HCCD, thereby slowing down the time it takes to perform this fast-dump operation.
Therefore, there is a need within the art to provide a fast-dump structure that can be used on devices with small pixel sizes while at the same time, being able to quickly clear charge from the main section of the array by avoiding the transfer of charge through the horizontal shift register(s).
The fast-dump structure is typically used within prior art devices in the transition area between the vertical and horizontal CCD as shown in FIG. 1. The fast dump can be used to selectively dump charge from the main array of the device before transfer is made into the horizontal register for effective and fast subsampling of the image. These structures can be located at every column of the vertical imaging section, or only at specific locations, (i.e., specific rows and/or columns), as predetermined at the time of design as described in U.S. Pat. No. 5,440,343. However, such prior art devices typically require a contact be made directly to the drain regions of each such structure, thereby putting obvious limitations on the cell sizes that can be realized for a given set of design rules. (Although other types of fast-dump structures exist that eliminate the need for a separate contact at each column, such as described in our U.S. Pat. No. 6,507,056 and shown in FIG. 2, these structures have the disadvantage that charge must be transferred through the horizontal shift register which slows down the process.)
The primary advantage of this new structure is that it does not require a separate contact to its drain region by using the existing drain of a lateral-overflow drain (LOD) antiblooming structure that is also typically used on full-frame CCD image sensors. (See, for example, U.S. Pat. No. 5,130,774.) By using the LOD as the drain, a separate opening in the gate electrode for the drain contact is avoided, thereby making the structure more compact. Gate control is provided by etching a hole in the CCD gate electrode over particular overflow channel regions of the LOD structure, and overlaying this with one of the subsequent gate electrode layers. This subsequent gate electrode is then used to control the fast-dump operation. The top view, cross-sectional views, and timing diagram for such a structure are shown in FIGS. 4 and 5a-5d. Although timing is shown for a two-phase CCD being operated with accumulation-mode clocking, it is to be understood that other types of CCDs and clocking schemes may be used.
Another advantage of this structure is that it does not require any additional masking or processing steps when built using a double (or more) electrode CCD process that employs a typical LOD structure.